/*****************************************************************************
 * hal_efm32lg_gpio.c
 *
 * Copyright (C) 2019 Jeasonvor <1101627719@qq.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 ****************************************************************************/

/*****************************************************************************
 * Included Files
 ****************************************************************************/

#include "plum_api.h"
#include "hal/source/hal_efm32lg/hal_efm32lg.h"

/*****************************************************************************
 * Trace Definitions
 ****************************************************************************/
#define LOG_RUN_LEVEL LOG_LEVEL_NONE
#define LOG_MODULE    "hal.gpio"
#include "thirdparty/log/log.h"
/*****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

#define HAL_EFM32_GPIO_PIN_INVALID  0xFFFF
#define HAL_EFM32_GPIO_PORT_INVALID 0xFFFF
/*****************************************************************************
 * Private Types
 ****************************************************************************/

typedef struct {
    plum_u32 id;
    plum_void (*irq_handle)(plum_u32 id);
    struct list_head list;
} hal_efm32lg_gpio_irq_t;

/*****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/

/*****************************************************************************
 * Private Data
 ****************************************************************************/

PLUM_PRIVATE hal_efm32lg_gpio_irq_t gpio_head;

/*****************************************************************************
 * Public Data
 ****************************************************************************/

/*****************************************************************************
 * Private Functions
 ****************************************************************************/

PLUM_PRIVATE
GPIO_Port_TypeDef hal_emf32_gpio_port(plum_u32 id)
{
    GPIO_Port_TypeDef port = HAL_EFM32_GPIO_PORT_INVALID;

    switch (PLUM_HAL_GPIO_PORT(id)) {
        case PLUM_HAL_ID_GPIO_A_BASE:
#if (_GPIO_PORT_A_PIN_COUNT > 0)
            port = gpioPortA;
#endif
            break;

        case PLUM_HAL_ID_GPIO_B_BASE:
#if (_GPIO_PORT_B_PIN_COUNT > 0)
            port = gpioPortB;
#endif
            break;

        case PLUM_HAL_ID_GPIO_C_BASE:
#if (_GPIO_PORT_C_PIN_COUNT > 0)
            port = gpioPortC;
#endif
            break;

        case PLUM_HAL_ID_GPIO_D_BASE:
#if (_GPIO_PORT_D_PIN_COUNT > 0)
            port = gpioPortD;
#endif
            break;

        case PLUM_HAL_ID_GPIO_E_BASE:
#if (_GPIO_PORT_E_PIN_COUNT > 0)
            port = gpioPortE;
#endif
            break;

        case PLUM_HAL_ID_GPIO_F_BASE:
#if (_GPIO_PORT_F_PIN_COUNT > 0)
            port = gpioPortF;
#endif
            break;

        case PLUM_HAL_ID_GPIO_G_BASE:
#if (_GPIO_PORT_G_PIN_COUNT > 0)
            port = gpioPortG;
#endif
            break;

        case PLUM_HAL_ID_GPIO_I_BASE:
#if (_GPIO_PORT_I_PIN_COUNT > 0)
            port = gpioPortI;
#endif
            break;

        case PLUM_HAL_ID_GPIO_J_BASE:
#if (_GPIO_PORT_J_PIN_COUNT > 0)
            port = gpioPortJ;
#endif
            break;

        case PLUM_HAL_ID_GPIO_K_BASE:
#if (_GPIO_PORT_K_PIN_COUNT > 0)
            port = gpioPortK;
#endif
            break;

        default:
            break;
    }

    return (port);
}

PLUM_PRIVATE
plum_u32 hal_efm32_gpio_pin(plum_u32 id)
{
    plum_u32 pin = PLUM_HAL_GPIO_PIN(id);

    switch (pin) {
        case 0:
        case 1:
        case 2:
        case 3:
        case 4:
        case 5:
        case 6:
        case 7:
        case 8:
        case 9:
        case 10:
        case 11:
        case 12:
        case 13:
        case 14:
        case 15:
            break;

        default:
            pin = HAL_EFM32_GPIO_PIN_INVALID;
            break;
    }

    return (pin);
}

PLUM_PRIVATE
plum_void hal_efm32_gpio_clk_enable(plum_void)
{
    /* enable clock */
    CMU_ClockEnable(cmuClock_HFPER, true);
    CMU_ClockEnable(cmuClock_GPIO, true);
}

PLUM_PRIVATE
plum_u32 hal_efm32_gpio_irq_line(plum_u32 pin)
{
    plum_s32 rc = PLUM_ECODE_OK;

    return (rc);
}

PLUM_PRIVATE
plum_s32 hal_efm32_goio_dir(plum_u32 id, plum_hal_gpio_com_cof_t cof)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        if (!PLUM_HAL_ID_IS_GPIO(id)) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        GPIO_Port_TypeDef port = hal_emf32_gpio_port(id);
        if (port == HAL_EFM32_GPIO_PORT_INVALID) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        uint32_t pin = hal_efm32_gpio_pin(id);
        if (pin == HAL_EFM32_GPIO_PIN_INVALID) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        /* set mode */
        GPIO_Mode_TypeDef mode;
        uint32_t          value = 1;
        switch (cof) {
            case PLUM_HAL_GPIO_MODE_INPUT:
            case PLUM_HAL_GPIO_MODE_ANALOG:
                mode = gpioModeInput;
                break;

            case PLUM_HAL_GPIO_MODE_INPUT_UP:
                value = 1;
                mode  = gpioModeInputPull;
                break;

            case PLUM_HAL_GPIO_MODE_INPUT_DOWN:
                value = 0;
                mode  = gpioModeInputPull;
                break;

            case PLUM_HAL_GPIO_MODE_OUT_PP:
                mode  = gpioModePushPull;
                value = 1;
                break;

            case PLUM_HAL_GPIO_MODE_OUT_OD:
                break;

            case PLUM_HAL_GPIO_MODE_OUT_OD_UP:
                break;

            case PLUM_HAL_GPIO_MODE_OUT_OD_DOWN:
                break;

            case PLUM_HAL_GPIO_MODE_AF_PP:
                break;

            case PLUM_HAL_GPIO_MODE_AF_OD:
                break;

            case PLUM_HAL_GPIO_MODE_AF_INPUT:
                break;

            default:
                break;
        }

        GPIO_PinModeSet(port, pin, mode, value);
    } while (0);

    return (rc);
}

PLUM_PRIVATE
hal_efm32lg_gpio_irq_t *hal_efm32_gpio_irq_node_apply(
    plum_u32 id, plum_void (*handler)(plum_u32 id))
{
    hal_efm32lg_gpio_irq_t *node = plum_null;

    do {
        if (!gpio_head.list.next) {
            INIT_LIST_HEAD(&gpio_head.list);
        }

        node = (hal_efm32lg_gpio_irq_t *)EFM32LG_MALLOC(
            sizeof(hal_efm32lg_gpio_irq_t));
        if (node) {
            memset(node, 0, sizeof(node));
            node->id         = id;
            node->irq_handle = handler;
        }
    } while (0);

    return (node);
}

PLUM_PRIVATE
hal_efm32lg_gpio_irq_t *hal_efm32_gpio_irq_node_find(plum_u32 id)
{
    hal_efm32lg_gpio_irq_t *node = plum_null;

    struct list_head *pos;
    list_for_each(pos, &gpio_head.list)
    {
        node = list_entry(pos, hal_efm32lg_gpio_irq_t, list);
        if (node->id == id) {
            break;
        }
    }

    return (node);
}

PLUM_PRIVATE
hal_efm32lg_gpio_irq_t *hal_efm32_gpio_irq_node_find_by_pin(plum_u32 pin)
{
    hal_efm32lg_gpio_irq_t *node = plum_null;

    struct list_head *pos;
    list_for_each(pos, &gpio_head.list)
    {
        node = list_entry(pos, hal_efm32lg_gpio_irq_t, list);
        if (PLUM_HAL_GPIO_PIN(node->id) == pin) {
            return (node);
        }
    }

    return (plum_null);
}

PLUM_PRIVATE
plum_void hal_efm32_gpio_irq_node_insert(hal_efm32lg_gpio_irq_t *node)
{
    list_add(&node->list, &gpio_head.list);
}

PLUM_PRIVATE
plum_void hal_efm32_gpio_irq_node_del(hal_efm32lg_gpio_irq_t *node)
{
    list_del(&node->list);

    EFM32LG_FREE(node);
}

PLUM_PRIVATE
plum_s32 hal_efm32_gpio_irq(plum_u32 id, plum_hal_gpio_irq_cof_t *cof)
{
    plum_s32 rc = PLUM_ECODE_OK;

    do {
        GPIO_Port_TypeDef port = hal_emf32_gpio_port(id);
        if (port == HAL_EFM32_GPIO_PORT_INVALID) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        uint32_t pin = hal_efm32_gpio_pin(id);
        if (pin == HAL_EFM32_GPIO_PIN_INVALID) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        bool risingEdge  = false;
        bool fallingEdge = false;
        if (cof->trip == PLUM_HAL_GPIO_IRQ_BOTH_EDGE) {
            fallingEdge = true;
            risingEdge  = true;
        }
        else if (cof->trip == PLUM_HAL_GPIO_IRQ_FALLING_EDGE) {
            fallingEdge = true;
        }
        else if (cof->trip == PLUM_HAL_GPIO_IRQ_RISING_EDGE) {
            risingEdge = true;
        }
        else {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        uint32_t irqline = hal_efm32_gpio_irq_line(id);

        GPIO_ExtIntConfig(port, pin, irqline, risingEdge, fallingEdge, true);

        GPIO_IntEnable(hal_efm32_gpio_irq_line(pin));

        hal_efm32lg_gpio_irq_t *node =
            hal_efm32_gpio_irq_node_apply(id, cof->irq_handle);
        if (!node) {
            rc = PLUM_ECODE_EMEM;
            break;
        }

        hal_efm32_gpio_irq_node_insert(node);

        if (pin % 2) {
            NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn);
            NVIC_EnableIRQ(GPIO_EVEN_IRQn);
        }
        else {
            NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
            NVIC_EnableIRQ(GPIO_ODD_IRQn);
        }
    } while (0);

    return (rc);
}

/*****************************************************************************
 * Callback Functions
 ****************************************************************************/

plum_void GPIO_EVEN_IRQHandler(plum_void)
{
    uint32_t iflags;

    /* Get all even interrupts. */
    iflags = GPIO_IntGetEnabled() & 0x00005555;

    /* Clean only even interrupts. */
    GPIO_IntClear(iflags);

    uint32_t pin = SL_CTZ(iflags);

    hal_efm32lg_gpio_irq_t *node = hal_efm32_gpio_irq_node_find_by_pin(pin);
    if (node) {
        /* call user callback */
        node->irq_handle(node->id);
    }
}

plum_void GPIO_ODD_IRQHandler(plum_void)
{
    uint32_t iflags;

    /* Get all odd interrupts. */
    iflags = GPIO_IntGetEnabled() & 0x0000AAAA;

    /* Clean only odd interrupts. */
    GPIO_IntClear(iflags);

    uint32_t pin = SL_CTZ(iflags);

    hal_efm32lg_gpio_irq_t *node = hal_efm32_gpio_irq_node_find_by_pin(pin);
    if (node) {
        /* call user callback */
        node->irq_handle(node->id);
    }
}
/*****************************************************************************
 * Public Functions
 ****************************************************************************/

PLUM_PUBLIC
plum_s32 plum_hal_gpio_init(plum_u32 id, plum_hal_gpio_cof_t *cof)
{
    plum_s32 rc = PLUM_ECODE_OK;

    hal_efm32_gpio_clk_enable();

    if (cof->mode == PLUM_HAL_GPIO_MODE_COMMON) {
        rc = hal_efm32_goio_dir(id, cof->config.com);
    }
    else if (cof->mode == PLUM_HAL_GPIO_MODE_IRQ) {
        rc = hal_efm32_gpio_irq(id, &cof->config.irq);
    }

    return (rc);
}

PLUM_PUBLIC
plum_bit plum_hal_gpio_read(plum_u32 id)
{
    plum_bit sta = plum_false;

    do {
        GPIO_Port_TypeDef port = hal_emf32_gpio_port(id);
        if (port == HAL_EFM32_GPIO_PORT_INVALID) {
            break;
        }

        uint32_t pin = hal_efm32_gpio_pin(id);
        if (pin == HAL_EFM32_GPIO_PIN_INVALID) {
            break;
        }

        GPIO_Mode_TypeDef mode = GPIO_PinModeGet(port, pin);
        switch (mode) {
            case gpioModeInput:
                sta = (plum_bit)GPIO_PinInGet(port, pin);
                break;

            case gpioModePushPull:
                sta = (plum_bit)GPIO_PinOutGet(port, pin);
                break;

            default:
                break;
        }
    } while (0);

    LOG_D("read gpio[0x%08X] value : %d", id, sta);
    return (sta);
}

PLUM_PUBLIC
plum_s32 plum_hal_gpio_write(plum_u32 id, plum_hal_gpio_sta_t sta)
{
    plum_s32 rc = PLUM_ECODE_OK;

    LOG_D("set gpio[0x%08X] value : %d", id, sta);
    do {
        GPIO_Port_TypeDef port = hal_emf32_gpio_port(id);
        if (port == HAL_EFM32_GPIO_PORT_INVALID) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        uint32_t pin = hal_efm32_gpio_pin(id);
        if (pin == HAL_EFM32_GPIO_PIN_INVALID) {
            rc = PLUM_ECODE_EPARA;
            break;
        }

        if (sta == PLUM_HAL_GPIO_TOG) {
            GPIO_PinOutToggle(port, pin);
        }
        else if (sta == PLUM_HAL_GPIO_LOW) {
            GPIO_PinOutClear(port, pin);
        }
        else if (sta == PLUM_HAL_GPIO_HIGH) {
            GPIO_PinOutSet(port, pin);
        }
    } while (0);

    return (rc);
}

/****************************************************************************/
/*                                                                          */
/*  End of file.                                                            */
/*                                                                          */
/****************************************************************************/
